library IEEE;
use IEEE.std_logic_1164.all;

entity syndrome is
  port (
	DU: IN STD_LOGIC_VECTOR (1 to 7);
    SYN: OUT STD_LOGIC_VECTOR (2 downto 0)	
	);
end syndrome;

architecture syndrome of syndrome is
begin
  SYN(0) <= DU(1) xor DU(3) xor DU(5) xor DU(7);
  SYN(1) <= DU(2) xor DU(3) xor DU(6) xor DU(7);
  SYN(2) <= DU(4) xor DU(5) xor DU(6) xor DU(7);
end syndrome;