library IEEE;
use IEEE.std_logic_1164.all;

entity mux4in18b is
    port (
        S: in STD_LOGIC_VECTOR (2 downto 0);       -- Select inputs, 0-7 ==> ABACADAB
        A, B, C, D: in STD_LOGIC_VECTOR (1 to 18); -- Data bus inputs
        Y: out STD_LOGIC_VECTOR (1 to 18)          -- Data bus output
    );
end mux4in18b;

architecture mux4in18p of mux4in18b is
begin
process(S, A, B, C, D)
variable i: INTEGER;
  begin
    case S is
      when "000" | "010" | "100" | "110" => Y <= A;
      when "001" | "111" => Y <= B;
      when "011" => Y <= C;
      when "101" => Y <= D;
      when others => Y <= (others => 'U');
    end case;
  end process;
end mux4in18p;