library IEEE;
use IEEE.std_logic_1164.all;

entity V74x138 is
    port (
        G1: in STD_LOGIC;
        G2A_L: in STD_LOGIC;
        G2B_L: in STD_LOGIC;
        A: in STD_LOGIC_VECTOR (2 downto 0);
        Y_L: out STD_LOGIC_VECTOR (0 to 7)
    );
end V74x138;

architecture V74x138_a of V74x138 is
  signal Y_L_i: STD_LOGIC_VECTOR (0 to 7);
begin
    with A select Y_L_i <=
      "01111111" when "000",
      "10111111" when "001",
      "11011111" when "010",
      "11101111" when "011",
      "11110111" when "100",
      "11111011" when "101",
      "11111101" when "110",
      "11111110" when "111",
      "11111111" when others;
    Y_L <= Y_L_i when (G1 and not G2A_L and not G2B_L)='1' else "11111111";
end V74x138_a;

architecture V74x138_b of V74x138 is
  signal G2A, G2B: STD_LOGIC;             -- active-high version of inputs
  signal Y_i: STD_LOGIC_VECTOR (0 to 7);  -- active-high version of outputs
  signal Y_s: STD_LOGIC_VECTOR (0 to 7);  -- internal signal
begin
    G2A <= not G2A_L; -- convert inputs
    G2B <= not G2B_L; -- convert inputs
    with A select Y_s <=
      "10000000" when "000",
      "01000000" when "001",
      "00100000" when "010",
      "00010000" when "011",
      "00001000" when "100",
      "00000100" when "101",
      "00000010" when "110",
      "00000001" when "111",
      "00000000" when others;
    Y_i <= not Y_s when (G1 and G2A and G2B)='1' else "00000000";
    Y_L <= Y_i;   -- convert outputs
end V74x138_b;

architecture V74x138_c of V74x138 is
  signal G2A, G2B: STD_LOGIC;             -- active-high version of inputs
  signal Y_i: STD_LOGIC_VECTOR (0 to 7);  -- active-high version of outputs
  component V3to8dec port (G1,G2A,G2B: in STD_LOGIC;
                           A: in STD_LOGIC_VECTOR (2 downto 0);
                           Y: out STD_LOGIC_VECTOR (0 to 7) ); end component;
begin
  G2A <= not G2A_L;   -- convert inputs
  G2B <= not G2B_L;   -- convert inputs
  Y_L <= not Y_i;     -- convert outputs
  U1: V3to8dec port map (G1, G2A, G2B, A, Y_i);
end V74x138_c;