library IEEE;
use IEEE.std_logic_1164.all;

entity V3to8dec is
    port (
        G1: in STD_LOGIC;
        G2: in STD_LOGIC;
        G3: in STD_LOGIC;
        A: in STD_LOGIC_VECTOR (2 downto 0);
        Y: out STD_LOGIC_VECTOR (0 to 7)
    );
end V3to8dec;

architecture V3to8dec_a of V3to8dec is
  signal Y_s: STD_LOGIC_VECTOR (0 to 7);  -- internal signal
begin
    with A select Y_s <=
      "10000000" when "000",
      "01000000" when "001",
      "00100000" when "010",
      "00010000" when "011",
      "00001000" when "100",
      "00000100" when "101",
      "00000010" when "110",
      "00000001" when "111",
      "00000000" when others;
    Y <= Y_s when (G1 and G2 and G3)='1'
             else "00000000";
end V3to8dec_a;